Presentation 1999/9/28
Circuit design of high speed and high density Chain FRAM
S. Watanabe, D. Takashima, S. Shuto, I. Kunishima, H. Takenaka, Y. Oowaki, S Tanaka,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Chain FRAM with nonvolatile and high speed operation has been developed. In order to verify the activity 16kb test chip has been fabricated. The test chip has achieved the fastest 37ns access time and 80ns cycle time so far reported, and also has realized 14% higher packing density.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Chain FRAM / FRAM / access time / nonvolatile / chip size
Paper # SDM99-155
Date of Issue

Conference Information
Committee SDM
Conference Date 1999/9/28(1days)
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Paper Information
Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Circuit design of high speed and high density Chain FRAM
Sub Title (in English)
Keyword(1) Chain FRAM
Keyword(2) FRAM
Keyword(3) access time
Keyword(4) nonvolatile
Keyword(5) chip size
1st Author's Name S. Watanabe
1st Author's Affiliation Research and Development Center, Toshiba Corporation()
2nd Author's Name D. Takashima
2nd Author's Affiliation Research and Development Center, Toshiba Corporation
3rd Author's Name S. Shuto
3rd Author's Affiliation Microelectonics Engineering Laboratory, Toshiba Corporation
4th Author's Name I. Kunishima
4th Author's Affiliation Microelectonics Engineering Laboratory, Toshiba Corporation
5th Author's Name H. Takenaka
5th Author's Affiliation Toshiba Microelectronics Corporation
6th Author's Name Y. Oowaki
6th Author's Affiliation Microelectonics Engineering Laboratory, Toshiba Corporation
7th Author's Name S Tanaka
7th Author's Affiliation Microelectonics Engineering Laboratory, Toshiba Corporation
Date 1999/9/28
Paper # SDM99-155
Volume (vol) vol.99
Number (no) 340
Page pp.pp.-
#Pages 6
Date of Issue