Presentation 1999/12/3
Reduced Parastic Inductances in BGA Package using Floating Conductive Plane
Tsuyoshi Ishihara, Tomo Yasuda, Hidetoshi Murakami, Masahiko Kobayashi, Toyohiko Kumakura,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We propose a new package structure, in which a floating conductive plane is placed under wiring patterns instead of a ground plane. This structure requires no vias and hence it can be realized with minimum cost increase. The proposed structure was adopted to a BGA package and its effect on parasitic inductances were measured and simulated. The effect on electrical characteristics was also simulated.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Ball Grid Array / Inductance / Conductive plane / S parameter / Electrical characteristics
Paper # CPM99-134
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Conference Information
Committee CPM
Conference Date 1999/12/3(1days)
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Paper Information
Registration To Component Parts and Materials (CPM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Reduced Parastic Inductances in BGA Package using Floating Conductive Plane
Sub Title (in English)
Keyword(1) Ball Grid Array
Keyword(2) Inductance
Keyword(3) Conductive plane
Keyword(4) S parameter
Keyword(5) Electrical characteristics
1st Author's Name Tsuyoshi Ishihara
1st Author's Affiliation Optoelectronic System Laboratory, Hitachi Cable, Ltd.()
2nd Author's Name Tomo Yasuda
2nd Author's Affiliation Electronic Material Engineering Department, Densen Works, Hitachi Cable, Ltd.
3rd Author's Name Hidetoshi Murakami
3rd Author's Affiliation Optoelectronic System Laboratory, Hitachi Cable, Ltd.
4th Author's Name Masahiko Kobayashi
4th Author's Affiliation Optoelectronic System Laboratory, Hitachi Cable, Ltd.
5th Author's Name Toyohiko Kumakura
5th Author's Affiliation Electronic Material Engineering Department, Densen Works, Hitachi Cable, Ltd.
Date 1999/12/3
Paper # CPM99-134
Volume (vol) vol.99
Number (no) 484
Page pp.pp.-
#Pages 8
Date of Issue