Presentation 1999/12/2
Fail pattern classification and analysis system of memory fail bit maps
A. Ito, K. Nakamae, H. Fujioka,
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Abstract(in English) We have developed the automatic system that classifies failure patterns from fail bit maps and estimates the causes of failure. The system consists of three steps, the macro level failure pattern classification, the micro level failure pattern classification and the cause estimation based on the comparison of two level classified results with the expert knowledge. In the macro and micro levels, the failure patterns are classified into five kinds and six kinds, respectively. The system also shows a short summary of the failure pattern distribution over the wafer. The system was applied to fail bit map data from recent DRAM devices to show its validity.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) fail bit map / failure pattern classification / failure distribution / cause estimation
Paper # CPM99-125
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Conference Information
Committee CPM
Conference Date 1999/12/2(1days)
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Registration To Component Parts and Materials (CPM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Fail pattern classification and analysis system of memory fail bit maps
Sub Title (in English)
Keyword(1) fail bit map
Keyword(2) failure pattern classification
Keyword(3) failure distribution
Keyword(4) cause estimation
1st Author's Name A. Ito
1st Author's Affiliation Department of Information Systems Engineering, Faculty of Engineering, Osaka University()
2nd Author's Name K. Nakamae
2nd Author's Affiliation Department of Information Systems Engineering, Faculty of Engineering, Osaka University
3rd Author's Name H. Fujioka
3rd Author's Affiliation Department of Information Systems Engineering, Faculty of Engineering, Osaka University
Date 1999/12/2
Paper # CPM99-125
Volume (vol) vol.99
Number (no) 483
Page pp.pp.-
#Pages 7
Date of Issue