Presentation | 1999/12/2 Chip Sliced Divider Using Redundant Binary Representation Kazuhiro Abe, Hiroshi Kasahara, Tsugio Nakamura, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Multiplier and divider used for specific hardware of public key cryptosystem arithmetic are constructed from many adders and subtracters for higher accuracy. But with the increase of accuracy, the accumulated arith-metic delay problem is unavoidable. There are some papers that show the redundant binary representation method is effective to cope with the problem. But there are no considerations for the problems of the rounding error and accurate remainder. This paper proposes a method that can cope with these problems, and can be expandable to any accuracy by inherent chip sliced architecture. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Redundant binary representation / Divider / Cascadable divider / Residue arithmetic / Chip slice |
Paper # | CPM99-123 |
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Committee | CPM |
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Conference Date | 1999/12/2(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Component Parts and Materials (CPM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Chip Sliced Divider Using Redundant Binary Representation |
Sub Title (in English) | |
Keyword(1) | Redundant binary representation |
Keyword(2) | Divider |
Keyword(3) | Cascadable divider |
Keyword(4) | Residue arithmetic |
Keyword(5) | Chip slice |
1st Author's Name | Kazuhiro Abe |
1st Author's Affiliation | Tokyo Denki University() |
2nd Author's Name | Hiroshi Kasahara |
2nd Author's Affiliation | Tokyo Denki University |
3rd Author's Name | Tsugio Nakamura |
3rd Author's Affiliation | Kokusai Junior College |
Date | 1999/12/2 |
Paper # | CPM99-123 |
Volume (vol) | vol.99 |
Number (no) | 483 |
Page | pp.pp.- |
#Pages | 7 |
Date of Issue |