Presentation 1999/10/29
Design of SFQ Fast Pallarel Adder and Multiplier
Kiyoshi Yanagisawa, Takeshi Onomi, Koji Nakajima, Akira Syoji,
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Abstract(in English) We propose the high-speed parallel adder and multiplier using SFQ. We have confirmed the operation of ICF gate which is a basis of the phase mode circuit. In this report, some gates based on the ICF gate were proposed, and the operation was confirmed experimentally. We report design and simulation result of adder and multiplier which are basis of DSP using those basic gates.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) adder / multiplier / ICF gate / SFQ / superconducting logic circuit
Paper # SCE99-30
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Conference Information
Committee SCE
Conference Date 1999/10/29(1days)
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Paper Information
Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of SFQ Fast Pallarel Adder and Multiplier
Sub Title (in English)
Keyword(1) adder
Keyword(2) multiplier
Keyword(3) ICF gate
Keyword(4) SFQ
Keyword(5) superconducting logic circuit
1st Author's Name Kiyoshi Yanagisawa
1st Author's Affiliation Research Institute of Electrical Communication, Tohoku University()
2nd Author's Name Takeshi Onomi
2nd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
3rd Author's Name Koji Nakajima
3rd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
4th Author's Name Akira Syoji
4th Author's Affiliation Electrotechnical Laboratory
Date 1999/10/29
Paper # SCE99-30
Volume (vol) vol.99
Number (no) 408
Page pp.pp.-
#Pages 6
Date of Issue