| Presentation | 1999/10/29 Timing Design of RSFQ Logic Circuits Using Verilog HDL N. Yoshikawa, Shizuka Mori, Junichi Koshiyama, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Logic level circuit simulation is strongly demanded in the design of large scale rapid single flux quantum (RSFQ) integrated circuits. However, it is not so easy because to make a standard library of RSFQ logic gates is difficult due to the smallness of their gain. In this report, we have investigated the way to conduct the logic level simulation of RSFQ circuits by Verilog HDL based on the cell based design methodology using binary decision diagram (BDD). In the simulation, we consider variations in timing parameters arising form the change of the bias current. The Verilog simulations of the RSFQ half adder indicate that the results precisely agree with the results calculated by an analog simulator and that the simulation time is reduced considerably. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RSFQ logic circuit / BDD / circuit simulation / HDL / superconductive integrated circuit |
| Paper # | SCE99-28 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 1999/10/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Timing Design of RSFQ Logic Circuits Using Verilog HDL |
| Sub Title (in English) | |
| Keyword(1) | RSFQ logic circuit |
| Keyword(2) | BDD |
| Keyword(3) | circuit simulation |
| Keyword(4) | HDL |
| Keyword(5) | superconductive integrated circuit |
| 1st Author's Name | N. Yoshikawa |
| 1st Author's Affiliation | Faculty of Engineering, Yokohama National University() |
| 2nd Author's Name | Shizuka Mori |
| 2nd Author's Affiliation | Faculty of Engineering, Yokohama National University |
| 3rd Author's Name | Junichi Koshiyama |
| 3rd Author's Affiliation | Faculty of Engineering, Yokohama National University |
| Date | 1999/10/29 |
| Paper # | SCE99-28 |
| Volume (vol) | vol.99 |
| Number (no) | 408 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |