Presentation 1999/11/26
A proposal to reduce design TAT for high speed ULSI using improved timing accuracy on timing simulator
Hiroshi Kawamoto,
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Abstract(in English) Due to the progress of device technology, deep sub-micron process enables not only to increase density but also to increase the internal clock frequencies year by year. As the clock speed increases, timing accuracy of timing simulation does not fit to the actual device operation timing. This mismatch causes long development period of the high speed ULSI. Currently, E-Beam Prober is considered merely as a failure analysis tool. This E-beam prober is used for measuring the internal node for comparing the actual timing with timing simulator. By comparing both simulation timing and actual timing of E-Beam, the difference is used for improving timing accuracy of simulation. By applying this methodology to the development of high speed Memory, the development period is reduced dramatically. This paper describes about the importance of improved timing simulator for high speed devices design.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) high speed device / timing simulation / operation verification / design Turn Around Time
Paper # CPSY99-80
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Conference Information
Committee CPSY
Conference Date 1999/11/26(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A proposal to reduce design TAT for high speed ULSI using improved timing accuracy on timing simulator
Sub Title (in English)
Keyword(1) high speed device
Keyword(2) timing simulation
Keyword(3) operation verification
Keyword(4) design Turn Around Time
1st Author's Name Hiroshi Kawamoto
1st Author's Affiliation EBT SE Section 1^ SE Division ATE SE Department ADVANTEST Corporation()
Date 1999/11/26
Paper # CPSY99-80
Volume (vol) vol.99
Number (no) 480
Page pp.pp.-
#Pages 8
Date of Issue