Presentation 1999/10/29
64Gbps 8×8 one-chip network switch: RHiNET-2/SW
Hiroaki Nishi, Kouji Tasyo, Shinji Nishimura, Tomohiro Kudoh, Hideharu Amano,
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Abstract(in English) The RHiNET (RWCP High Performance Network) system which supports an effective parallel processing by connecting PC's distributed in one or more floors of a building is proposed. RHiNET system includes network interfaces fit PCs' I/O bus, the high speed switches, and optical interconnections which connect between them. In this paper, the architecture and design of 8×8 8Gbps/port one-chip switch CMOS ASIC RHiNET-2/SW is described. A simulation results of its performance is also shown.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Network / Optical Interconnect / Structured buffer pool / High performance computing
Paper # CPSY99-76
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Committee CPSY
Conference Date 1999/10/29(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 64Gbps 8×8 one-chip network switch: RHiNET-2/SW
Sub Title (in English)
Keyword(1) Network
Keyword(2) Optical Interconnect
Keyword(3) Structured buffer pool
Keyword(4) High performance computing
1st Author's Name Hiroaki Nishi
1st Author's Affiliation Real World Computing Partnership()
2nd Author's Name Kouji Tasyo
2nd Author's Affiliation Synergetech Inc.
3rd Author's Name Shinji Nishimura
3rd Author's Affiliation Real World Computing Partnership
4th Author's Name Tomohiro Kudoh
4th Author's Affiliation Real World Computing Partnership
5th Author's Name Hideharu Amano
5th Author's Affiliation Dept. of Comp. Sci. Keio University
Date 1999/10/29
Paper # CPSY99-76
Volume (vol) vol.99
Number (no) 409
Page pp.pp.-
#Pages 8
Date of Issue