| Presentation | 2000/1/12 Design on FPAccA model 2.0 Chip : Reconfigurable Floating-Point-Unit Array Yoichi KAWANO, Hiroyuki OCHI, Takao TSUDA, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Field Programmable Accumulator Array(FPAccA), a coarse-grain FPGA architecture, has been proposed to solve problems with conventional FPGAs such as increasing time taken for placement and routing. In this paper, FPAccA model 2.0 chip is designed and evaluated, which has a single-presision floating-point unit of IEEE 754 standard in each cell. Nine adders and three multipliers are implemented with 4.9 mm × 4.9 mm die size using 0.35μm triple-metal CMOS process. Expected peak performance is 300 MFLOPS at 100 MHz clock flequency. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPAccA / FPGA Architecture / Reconfigurable System / Floating-Point Unit / Chip Design Experiments |
| Paper # | VLD99-103,CPSY99-112 |
| Date of Issue |
| Conference Information | |
| Committee | CPSY |
|---|---|
| Conference Date | 2000/1/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Computer Systems (CPSY) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design on FPAccA model 2.0 Chip : Reconfigurable Floating-Point-Unit Array |
| Sub Title (in English) | |
| Keyword(1) | FPAccA |
| Keyword(2) | FPGA Architecture |
| Keyword(3) | Reconfigurable System |
| Keyword(4) | Floating-Point Unit |
| Keyword(5) | Chip Design Experiments |
| 1st Author's Name | Yoichi KAWANO |
| 1st Author's Affiliation | Department of Computer Engineering Faculty of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Hiroyuki OCHI |
| 2nd Author's Affiliation | Department of Computer Engineering Faculty of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Takao TSUDA |
| 3rd Author's Affiliation | Department of Computer Engineering Faculty of Information Sciences, Hiroshima City University |
| Date | 2000/1/12 |
| Paper # | VLD99-103,CPSY99-112 |
| Volume (vol) | vol.99 |
| Number (no) | 532 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |