| Presentation | 2000/1/12 A Non-Scan DFT Method for RTL Circuits Based on Fixed-Control Testability Shintaro NAGAI, Hiroki WADA, Satoshi OHTAKE, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we present a non-scan DFT method with complete fault efficiency for RTL circuits. An RTL circuit generally consists of a controller and a data path. The controller and the data path are connected with internal signals: control signals and status signals. We apply non-scan DFTs in the controller and in the data path, respectively. For the controller, we apply our DFT method which add an invalid state test generator to the controller. For the data path, test generation is based on hierarchical test generation. We introduce a new testability called"fixed-control testability"in order to generate a test plan for every combinational module. A test plan consist of three phases: justification, test and propagation phase. For fixed-control testability, each phase of test plan is composed of only one vector. Therefore, the test plan generator for the data path can be designed with combinational logic. Our experimental result show that the proposed method can reduce significantly both of test generation time and test application time compared with the full-scan design, though the hardware overhead of our method is slightly as same as that of the full-scan design. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RTL circuit / hierarchical test generation / test plan / fixed-control testability |
| Paper # | VLD99-101,CPSY99-110 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2000/1/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Non-Scan DFT Method for RTL Circuits Based on Fixed-Control Testability |
| Sub Title (in English) | |
| Keyword(1) | RTL circuit |
| Keyword(2) | hierarchical test generation |
| Keyword(3) | test plan |
| Keyword(4) | fixed-control testability |
| 1st Author's Name | Shintaro NAGAI |
| 1st Author's Affiliation | Graduate School of Information Science Nara Institute of Science and Technology() |
| 2nd Author's Name | Hiroki WADA |
| 2nd Author's Affiliation | Graduate School of Information Science Nara Institute of Science and Technology |
| 3rd Author's Name | Satoshi OHTAKE |
| 3rd Author's Affiliation | Graduate School of Information Science Nara Institute of Science and Technology |
| 4th Author's Name | Hideo FUJIWARA |
| 4th Author's Affiliation | Graduate School of Information Science Nara Institute of Science and Technology |
| Date | 2000/1/12 |
| Paper # | VLD99-101,CPSY99-110 |
| Volume (vol) | vol.99 |
| Number (no) | 532 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |