Presentation	2000/1/12 Scheduling and Placement of Operations Considering Data Communication Time Masaki NAKANO, Kazuhito ITO,
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Abstract(in English)	With the development of deep submicron technology, wire delay on an LSI chip is becoming relatively larger than gate delay. In LSI design, it is necessary to turn around the design if delay violates speed requirement. In order to reduce the turn around, wire delay determined by placement and routing must be considered even in high-level design. In this paper we propose a method to achieve high speed processing for a given processing algorithm by performing shceduling and placement of operations simultaneously. With this method wire delay based on the placement is precisely considered and may be minimized during the scheduling of operations.
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Keyword(in English)	LSI design / operation scheduling / placement / wire delay
Paper #	VLD99-100,CPSY99-109
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Conference Information
Committee	CPSY
Conference Date	2000/1/12(1days)
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Paper Information
Registration To	Computer Systems (CPSY)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Scheduling and Placement of Operations Considering Data Communication Time
Sub Title (in English)
Keyword(1)	LSI design
Keyword(2)	operation scheduling
Keyword(3)	placement
Keyword(4)	wire delay
1st Author's Name	Masaki NAKANO
1st Author's Affiliation	Department of Electrical and Electronic Systems, Saitama University()
2nd Author's Name	Kazuhito ITO
2nd Author's Affiliation	Department of Electrical and Electronic Systems, Saitama University
Date	2000/1/12
Paper #	VLD99-100,CPSY99-109
Volume (vol)	vol.99
Number (no)	532
Page	pp.pp.-
#Pages	8
Date of Issue