Presentation	2000/1/12 CPLD design by A High-Level Synthesis System Shin NAKAJO, Hiroshi KAWAKAMI, Ryo DANG,
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Abstract(in English)	This paper presents a High-Level Synthesis and examples of CPLD design by this system. This system takes as input behavioral description written by Verilog-HDL and outputs RTL description information of data path circuit and state machine circuit written by Verilog-HDL. RTL description is obtained from RTL information is ready to be used for logic synthesis, therefore we gain results which satisfy input behavioral description at timing analysis after layout. This system has an arithmetic operation unit, an ALU and a comparator, all with 32bit single precision.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	High-Level Synthesis / CPLD / statemachine
Paper #	VLD99-97,CPSY99-106
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Conference Information
Committee	CPSY
Conference Date	2000/1/12(1days)
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Paper Information
Registration To	Computer Systems (CPSY)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	CPLD design by A High-Level Synthesis System
Sub Title (in English)
Keyword(1)	High-Level Synthesis
Keyword(2)	CPLD
Keyword(3)	statemachine
1st Author's Name	Shin NAKAJO
1st Author's Affiliation	Hosei University()
2nd Author's Name	Hiroshi KAWAKAMI
2nd Author's Affiliation	Hosei University
3rd Author's Name	Ryo DANG
3rd Author's Affiliation	Hosei University
Date	2000/1/12
Paper #	VLD99-97,CPSY99-106
Volume (vol)	vol.99
Number (no)	532
Page	pp.pp.-
#Pages	6
Date of Issue