| Presentation | 2000/3/17 On Sectionalization of Trellis for Block Codes Hideki YAGI, Tomotsugu OKADA, Manabu KOBAYASHI, Shigeichi HIRASAWA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | H.T.Moorthy, S.Lin and G.T.Uehara have proposed a trellis construction method which is based on the IC implementation of Vitervi decoder and also shown that we can speed up a decoding time of given received sequences with this trellis. Even though the trellis is nonminimal and the total number of states increases, if the maximam number of states of each time axis is equal to or smaller than that of the minimal trellis, they have proved that the decoding speed of each parallel component is faster than that of the minimal trellis. However this method can construct only trellis where the section boundaries are decided beforehand. In this paper, we propose a new trellis sectionalization method, where the trellis has many parallel components, based on optimal sectionalization. We also show that we can effectively carry out the parallel implementation of a decoder so that we can reduse a decoding time by means of it. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | trellis / nonminimal trellis / parallel component / sectionalization of trellis / block code / Vitervi decoder |
| Paper # | IT99-97,ISEC99-136,SST99-145 |
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| Conference Information | |
| Committee | IT |
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| Conference Date | 2000/3/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Information Theory (IT) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On Sectionalization of Trellis for Block Codes |
| Sub Title (in English) | |
| Keyword(1) | trellis |
| Keyword(2) | nonminimal trellis |
| Keyword(3) | parallel component |
| Keyword(4) | sectionalization of trellis |
| Keyword(5) | block code |
| Keyword(6) | Vitervi decoder |
| 1st Author's Name | Hideki YAGI |
| 1st Author's Affiliation | Dep.of Industrial and Management Systems Engineering Waseda University() |
| 2nd Author's Name | Tomotsugu OKADA |
| 2nd Author's Affiliation | Dep.of Industrial and Management Systems Engineering Waseda University |
| 3rd Author's Name | Manabu KOBAYASHI |
| 3rd Author's Affiliation | Dep.of Industrial and Management Systems Engineering Waseda University |
| 4th Author's Name | Shigeichi HIRASAWA |
| 4th Author's Affiliation | Dep.of Industrial and Management Systems Engineering Waseda University |
| Date | 2000/3/17 |
| Paper # | IT99-97,ISEC99-136,SST99-145 |
| Volume (vol) | vol.99 |
| Number (no) | 700 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |