| Presentation | 2000/2/9 Silicon Stacked Transistor for PLEDM T. Kisu, K. Nakazato, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently we have proposed a new high-speed and high-density memory PLEDM.PLEDM cell consists of stacked transistor, PLEDTR, and MOSFET to amplify the stored data.Since this cell has gain, a large capacitor is not necessary.Silicon stacked transistors PLEDTRs have been fabricated on silicon dioxide using standard 0.2mm silicon process, and have shown good transistor characteristics. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RAM / Gain-cell / PLED / Vertical transistor / Tunnel barrier |
| Paper # | ED99-292,SDM99-185 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 2000/2/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Silicon Stacked Transistor for PLEDM |
| Sub Title (in English) | |
| Keyword(1) | RAM |
| Keyword(2) | Gain-cell |
| Keyword(3) | PLED |
| Keyword(4) | Vertical transistor |
| Keyword(5) | Tunnel barrier |
| 1st Author's Name | T. Kisu |
| 1st Author's Affiliation | Hitachi ULSI Systems Co., Ltd.() |
| 2nd Author's Name | K. Nakazato |
| 2nd Author's Affiliation | Hitachi Cambridge Laboratory, Hitachi Europe Ltd. |
| Date | 2000/2/9 |
| Paper # | ED99-292,SDM99-185 |
| Volume (vol) | vol.99 |
| Number (no) | 615 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |