| Presentation | 2000/3/17 Threshold voltage shift in 0.1μm self-aligned-gate GaAs-MESFETs under bians stress and prediction of their life time K. YOSHINO FUKAI, Kimiyoshi YAMASAKI, Kazumi NISHIMURA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Bias-temperature stress examinations of self-aligned 0.1μm-length gate GaAs-MESFETs have revealed a shift of threshold voltage related to Si doping concentration near the gate sides next to the channel region. With lowering doping concentration, the increase in threshold voltage in FETs goes faster and a 100-mV increase leads to a 20% reduction of operation speed in digital ICs after forward-biased storage at 200℃. The recovery of threshold voltage and the performance of digital ICs under reverse-biased stresses was observed. The degradation is released by increasing Si doping concentration as high as it can be set without causing serious reduction of breakdown voltage. We obtained the prediction of a median life exceeding 10^6 hours at 100℃ by setting the Si dose of 4.0 × 10^13 cm^-2. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | GaAs-MESFETs / self-aligned 0.1 μm-length gate / bias-temperature stress / threshold voltage / life time |
| Paper # | R99-43,CPM99-166 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2000/3/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Assistant | |
| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Threshold voltage shift in 0.1μm self-aligned-gate GaAs-MESFETs under bians stress and prediction of their life time |
| Sub Title (in English) | |
| Keyword(1) | GaAs-MESFETs |
| Keyword(2) | self-aligned 0.1 μm-length gate |
| Keyword(3) | bias-temperature stress |
| Keyword(4) | threshold voltage |
| Keyword(5) | life time |
| 1st Author's Name | K. YOSHINO FUKAI |
| 1st Author's Affiliation | NTT Photonics Laboratories() |
| 2nd Author's Name | Kimiyoshi YAMASAKI |
| 2nd Author's Affiliation | NTT Electronics Corpration |
| 3rd Author's Name | Kazumi NISHIMURA |
| 3rd Author's Affiliation | NTT Electronics Corpration |
| Date | 2000/3/17 |
| Paper # | R99-43,CPM99-166 |
| Volume (vol) | vol.99 |
| Number (no) | 712 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |