Presentation 2002/3/13
Analog neural-network associative memories with symmetrically connected CMOS synapses
Kazuhiko NAKAZAWA, Akira HIROSE,
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Abstract(in English) Analog neural network hardware has many advantages such as quicker response and smaller chip area over digital or pulse hardware. However, it is not widely investigated because it has been considered to have drawbacks in synaptic weight precision and noise. In order to overcome the problems, we propose novel designs: (l)a quick-response synaptic weight with high symmetry in both small-signal and large-amplitude operation and (2)an open-loop, quick-response and parallel-symmetric neuron circuit that has inverse and non-inverse output with high symmetry in delay and amplitude. We report the fabrication of an associative memory chip and its characteristics.
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Keyword(in English) Neurochip / Analog neural network / Symmetry / Synaptic resistor
Paper # NC2001-219
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Committee NC
Conference Date 2002/3/13(1days)
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Registration To Neurocomputing (NC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Analog neural-network associative memories with symmetrically connected CMOS synapses
Sub Title (in English)
Keyword(1) Neurochip
Keyword(2) Analog neural network
Keyword(3) Symmetry
Keyword(4) Synaptic resistor
1st Author's Name Kazuhiko NAKAZAWA
1st Author's Affiliation Department of Electronics Engineering, Graduate School of Engineering, The University of Tokyo()
2nd Author's Name Akira HIROSE
2nd Author's Affiliation Department of Frontier Informatics, Graduate School of Frontier Sciences, The University of Tokyo
Date 2002/3/13
Paper # NC2001-219
Volume (vol) vol.101
Number (no) 737
Page pp.pp.-
#Pages 8
Date of Issue