Presentation 2002/3/13
An Implementation Method of Pulsed Neuron Model for FPGA Devices
Nobuyoshi FUTAMATA, Susumu KUROYANAGI, Akira IWATA,
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Abstract(in English) We have been studied about the pulsed neural networks which are suitable for temporal information processing. The pulsed neural networks have very simple structure and don't need a multiplier for implementaion. In this article, we proposed an implementation method of a pulsed neural network for the FPGA devices. By apply this method, we can implement many pulsed neuron model in a FPGA device. We implemented pulsed neuron modules for sound localization and went through the realtime processing of them on a FPGA device.
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Keyword(in English) Pulsed Neuron / Digital Circuit / FPGA / ITD Extraction Model
Paper # NC2001-211
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Committee NC
Conference Date 2002/3/13(1days)
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Registration To Neurocomputing (NC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Implementation Method of Pulsed Neuron Model for FPGA Devices
Sub Title (in English)
Keyword(1) Pulsed Neuron
Keyword(2) Digital Circuit
Keyword(3) FPGA
Keyword(4) ITD Extraction Model
1st Author's Name Nobuyoshi FUTAMATA
1st Author's Affiliation Dept. of Electrical and Computer Eng., Nagoya Institute of Technology()
2nd Author's Name Susumu KUROYANAGI
2nd Author's Affiliation Dept. of Electrical and Computer Eng., Nagoya Institute of Technology
3rd Author's Name Akira IWATA
3rd Author's Affiliation Dept. of Electrical and Computer Eng., Nagoya Institute of Technology
Date 2002/3/13
Paper # NC2001-211
Volume (vol) vol.101
Number (no) 737
Page pp.pp.-
#Pages 8
Date of Issue