| Presentation | 2002/3/13 Logical function extraction from Neural Network : Increasing in efficiency of learning And Making hardware Satomi AMANO, Arata MIYAUCHI, Tomo ISHIKAWA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have proposed the technique of not using multiplication and addition. By the result of the recognition experiment by this method, we had checked that recognition time was shortened. However, by this method, the learning for acquiring the value suitable for extraction of the logical function took time. Therefore, we propose the technique of aiming at improvement in learning efficiency in this thesis. This technique uses the learning algorithm suitable for extracting a logical function, when learning. This is the technique of learning by newly setting the middle layer's evaluation value. By this result, we had checked that learning time had been shortened and the rate of extraction of the right logical function had increased. Moreover, The recognition system by this technique can be made only from a primitive logical operator. The system by this technology was actually compared with the system by general technology, and it had checked that the system by this technology was simpler. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multi-layered neural network / logical function |
| Paper # | NC2001-209 |
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| Committee | NC |
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| Conference Date | 2002/3/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Neurocomputing (NC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Logical function extraction from Neural Network : Increasing in efficiency of learning And Making hardware |
| Sub Title (in English) | |
| Keyword(1) | multi-layered neural network |
| Keyword(2) | logical function |
| 1st Author's Name | Satomi AMANO |
| 1st Author's Affiliation | Electrical Engineering, Graduate School, Musashi Institute of Technology() |
| 2nd Author's Name | Arata MIYAUCHI |
| 2nd Author's Affiliation | Electrical Engineering, Graduate School, Musashi Institute of Technology |
| 3rd Author's Name | Tomo ISHIKAWA |
| 3rd Author's Affiliation | Electrical Engineering, Graduate School, Musashi Institute of Technology |
| Date | 2002/3/13 |
| Paper # | NC2001-209 |
| Volume (vol) | vol.101 |
| Number (no) | 737 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |