Presentation 2005-09-15
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
Zhangcai HUANG, Atsushi KUROKAWA, Yasuaki INOUE,
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Abstract(in English) In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of the interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating Ceff of interconnect load for gate slew. The simulation results demonstrate a significant improvement in accuracy.
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Keyword(in English) Static Timing Analysis / Gate Slew / Effective Capacitance / Interconnect Loads
Paper # CAS2005-31,NLP2005-44
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Committee NLP
Conference Date 2005/9/8(1days)
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Registration To Nonlinear Problems (NLP)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
Sub Title (in English)
Keyword(1) Static Timing Analysis
Keyword(2) Gate Slew
Keyword(3) Effective Capacitance
Keyword(4) Interconnect Loads
1st Author's Name Zhangcai HUANG
1st Author's Affiliation The Graduate School of Information, Production and Systems, Waseda University()
2nd Author's Name Atsushi KUROKAWA
2nd Author's Affiliation The Semiconductor Technology Academic Research Center (STAC)
3rd Author's Name Yasuaki INOUE
3rd Author's Affiliation The Graduate School of Information, Production and Systems, Waseda University
Date 2005-09-15
Paper # CAS2005-31,NLP2005-44
Volume (vol) vol.105
Number (no) 276
Page pp.pp.-
#Pages 6
Date of Issue