| Presentation | 2002/3/8 FPGA Implementation of a Cellular Automata by using Verilog-HDL Hiroaki HAMABE, Kenya JIN'NO, Haruo HIROSE, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this article, an FPGA implementation circuit of two dimensional cellular automata is designed by Verilog-HDL which is High-level Description Language for digital circuit design. The cellular automata consist with 25 automata that each automation is arranged in 5×5 square. By using this system, an associative memory is proposed, and we confirm its association ability. The state transition rule of the cellular automata set on local auto-correlation learning of desired memories. This system is related to a discrete-time cellular neural network. As the result, it is a fundamental of implementation of large scale neural networks. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | cellular automata / FPGA / Veriog-HDL / neural network / associative memory |
| Paper # | NLP2001-102 |
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| Conference Information | |
| Committee | NLP |
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| Conference Date | 2002/3/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA Implementation of a Cellular Automata by using Verilog-HDL |
| Sub Title (in English) | |
| Keyword(1) | cellular automata |
| Keyword(2) | FPGA |
| Keyword(3) | Veriog-HDL |
| Keyword(4) | neural network |
| Keyword(5) | associative memory |
| 1st Author's Name | Hiroaki HAMABE |
| 1st Author's Affiliation | Department of Electrical and Electronics Engineering, Nippon Institute of Technology() |
| 2nd Author's Name | Kenya JIN'NO |
| 2nd Author's Affiliation | Department of Electrical and Electronics Engineering, Nippon Institute of Technology |
| 3rd Author's Name | Haruo HIROSE |
| 3rd Author's Affiliation | Department of Electrical and Electronics Engineering, Nippon Institute of Technology |
| Date | 2002/3/8 |
| Paper # | NLP2001-102 |
| Volume (vol) | vol.101 |
| Number (no) | 723 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |