Presentation | 2005-08-19 0.5V Asymmetric Three-Tr. Cell(ATC) DRAM Using 90nm Generic CMOS Logic Process Motoi ICHIHASHI, Haruki TODA, Yasuo ITOH, Koichiro ISHIBASHI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Asymmetric Three-Tr. Cell (ATC) DRAM which has one P- and two N-MOS transistors for one unit cell is proposed with "forced feedback sense amplifier" and "write echo refresh". Memory array of ATC DRAM operates at 0.5V and use only logic process with no additional process. A test chip on 90nm technology dissipates 180μA in refresh current at 1μs cycle refresh on 1Mb. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | DRAM / embedded memory |
Paper # | SDM2005-151,ICD2005-90 |
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Committee | ICD |
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Conference Date | 2005/8/12(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | 0.5V Asymmetric Three-Tr. Cell(ATC) DRAM Using 90nm Generic CMOS Logic Process |
Sub Title (in English) | |
Keyword(1) | DRAM |
Keyword(2) | embedded memory |
1st Author's Name | Motoi ICHIHASHI |
1st Author's Affiliation | STARC (Semiconductor Technology Academic Research Center):Renesas Technology() |
2nd Author's Name | Haruki TODA |
2nd Author's Affiliation | STARC (Semiconductor Technology Academic Research Center):Toshiba Corp. Semicoductor Company |
3rd Author's Name | Yasuo ITOH |
3rd Author's Affiliation | STARC (Semiconductor Technology Academic Research Center):Toshiba Microelecronics |
4th Author's Name | Koichiro ISHIBASHI |
4th Author's Affiliation | STARC (Semiconductor Technology Academic Research Center):Renesas Technology |
Date | 2005-08-19 |
Paper # | SDM2005-151,ICD2005-90 |
Volume (vol) | vol.105 |
Number (no) | 235 |
Page | pp.pp.- |
#Pages | 5 |
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