Presentation 2005-08-18
Isolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits
Daisuke KOSAKA, Makoto NAGATA, Yoshitaka MURASAKA, Atsushi IWATA,
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Abstract(in English) A deep n-well guard-ring, DNW-GR, provides effective isolation from substrate-coupled high frequency noises in combination with high-resistive p-type substrates. AC-measurements of S21 with port geometry and guard-ring structure dependencies are reported in a 0.25-μm CMOS standard mixed-signal technology with p-type substrates having the bulk resistivity from 10Ωcm to 3kΩcm. It is shown that DNW-GR on a 1-kΩcm substrate gains 20dB improvement in isolation against 1GHz coupling, compared with a p+ guard-ring on a standard 10Ωcm substrate. S21 simulations with substrate equivalent circuit models derived by way of F-matrix computation on test structures are in good agreement with measurements for a frequency range over 5GHz. The substrate models can compactly as well as precisely include layout-level isolation effects in circuit simulations for a mixed-signal/RF design.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) substrate crosstalk / deep n-well / high-resistive substrate / F-matrix computation / transmission characteristic
Paper # SDM2005-136,ICD2005-75
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Conference Date 2005/8/11(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Isolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits
Sub Title (in English)
Keyword(1) substrate crosstalk
Keyword(2) deep n-well
Keyword(3) high-resistive substrate
Keyword(4) F-matrix computation
Keyword(5) transmission characteristic
1st Author's Name Daisuke KOSAKA
1st Author's Affiliation Graduate School of Science and Technology, Kobe University, Department of Computer and Systems Engineering, Kobe University()
2nd Author's Name Makoto NAGATA
2nd Author's Affiliation Graduate School of Science and Technology, Kobe University, Department of Computer and Systems Engineering, Kobe University
3rd Author's Name Yoshitaka MURASAKA
3rd Author's Affiliation A-R-Tec Corporation
4th Author's Name Atsushi IWATA
4th Author's Affiliation A-R-Tec Corporation
Date 2005-08-18
Paper # SDM2005-136,ICD2005-75
Volume (vol) vol.105
Number (no) 234
Page pp.pp.-
#Pages 5
Date of Issue