| Presentation | 2005/7/29 A Study on High Speed and Low Power Interconnect Architecture of FPGAs Hiroyuki TANAKA, Yoshiki YAMAGUCHI, Ikuo YOSHIHARA, Moritoshi YASUNAGA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It is well known that the performance of FPGAs is largely dominated by their programmable interconnect. Many programmable switches are used in the interconnect and degrade the speed performance. In addition, they have large parasitic capacitance that causes excessive dynamic power dissipation. Consequently, it is important to improve the programmable interconnect architecture for the better performance of FPGAs in terms of delay and power. In this paper it is shown that there exists tradeoff between delay and power of programmable switches. We propose a new architecture of the programmable switches of FPGA interconnect, which are reconfigurable in respect of delay and power. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / interconnect / active switch / delay / power |
| Paper # | CPSY2005-23 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2005/7/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study on High Speed and Low Power Interconnect Architecture of FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | interconnect |
| Keyword(3) | active switch |
| Keyword(4) | delay |
| Keyword(5) | power |
| 1st Author's Name | Hiroyuki TANAKA |
| 1st Author's Affiliation | Graduate School of Systems and Information Engineering, University of Tsukuba() |
| 2nd Author's Name | Yoshiki YAMAGUCHI |
| 2nd Author's Affiliation | Graduate School of Systems and Information Engineering, University of Tsukuba |
| 3rd Author's Name | Ikuo YOSHIHARA |
| 3rd Author's Affiliation | Faculty of Engineering, University of Miyazaki |
| 4th Author's Name | Moritoshi YASUNAGA |
| 4th Author's Affiliation | Graduate School of Systems and Information Engineering, University of Tsukuba |
| Date | 2005/7/29 |
| Paper # | CPSY2005-23 |
| Volume (vol) | vol.105 |
| Number (no) | 226 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |