| Presentation | 2005/7/29 Behavior Analysis for Delinquent Loads Hideki MIWA, Yasuhiro DOUGO, Koji INOUE, Kazuaki MURAKAMI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, the performance of microprocessors has been improved extremely. On the other hand, DRAMs, commonly used as the main memory, is about 100 times as slow as microprocessors. In this situation, DRAMs suppress the performance of microprocessors. This problem is commonly called Memory Wall Problem. For the performance improvement of computer systems, it is very important to solve this problem. Currently, the authors are developing cache miss penalty reduction techniques focused on the delinquent loads which cause the cache misses frequently. Such load instructions are responsible for 90% of all the cache misses, and deteriorate the performance. In this paper, to reveal the cause of cache misses, the authors investigate the memory access patterns for several benchmark programs. The results show that almost all of the data which cause cache misses had been written to memory system by store instructions. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | cache memory / memory wall problem / cache miss penalty reduction / delinquent load instructions |
| Paper # | CPSY2005-22 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2005/7/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Behavior Analysis for Delinquent Loads |
| Sub Title (in English) | |
| Keyword(1) | cache memory |
| Keyword(2) | memory wall problem |
| Keyword(3) | cache miss penalty reduction |
| Keyword(4) | delinquent load instructions |
| 1st Author's Name | Hideki MIWA |
| 1st Author's Affiliation | Dept. of Informatics, Kyushu University() |
| 2nd Author's Name | Yasuhiro DOUGO |
| 2nd Author's Affiliation | Dept. of Electronics Engineering, Fukuoka University |
| 3rd Author's Name | Koji INOUE |
| 3rd Author's Affiliation | Dept. of Informatics, Kyushu University |
| 4th Author's Name | Kazuaki MURAKAMI |
| 4th Author's Affiliation | Dept. of Informatics, Kyushu University |
| Date | 2005/7/29 |
| Paper # | CPSY2005-22 |
| Volume (vol) | vol.105 |
| Number (no) | 226 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |