Presentation 2005/7/29
The efficient realization approach of a NFA pattern matching circuit with data compression technique
Masato ONO, Toshihiro KATASHITA, Atushi MAEDA, Yoshinori YAMAGUCHI,
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Abstract(in English) Recently, some network intrusion detection systems (NIDS) are developed with software such as Snort. As increasing the network speed, processing speed of pattern matching has become insufficient for processing all of intrusion rules. We propose an architecture based on a software-hardware cooperation. In this paper, we propose a compact NFA based pattern matching circuit with data compression technique. This circuit is 29.6% smaller than conventional technique for 2048 pattern.
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Keyword(in English) Intrusion Detection System / FPGA / Hardware/Software cooperation
Paper # CPSY2005-21
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Committee CPSY
Conference Date 2005/7/29(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) The efficient realization approach of a NFA pattern matching circuit with data compression technique
Sub Title (in English)
Keyword(1) Intrusion Detection System
Keyword(2) FPGA
Keyword(3) Hardware/Software cooperation
1st Author's Name Masato ONO
1st Author's Affiliation Graduate School of System and Information Technology, University of Tsukuba()
2nd Author's Name Toshihiro KATASHITA
2nd Author's Affiliation Graduate School of System and Information Technology, University of Tsukuba
3rd Author's Name Atushi MAEDA
3rd Author's Affiliation Graduate School of System and Information Technology, University of Tsukuba
4th Author's Name Yoshinori YAMAGUCHI
4th Author's Affiliation Graduate School of System and Information Technology, University of Tsukuba
Date 2005/7/29
Paper # CPSY2005-21
Volume (vol) vol.105
Number (no) 226
Page pp.pp.-
#Pages 6
Date of Issue