| Presentation | 2005-09-09 The study of the high frequency electrical characteristics in high-speed digital device mounting : The Characteristic of high speed transmission of Flip-Chip Mounting Chihiro Ueda, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, using 3D EM simulator, we studied transient characteristics of high frequency current in SIP & SOC packages to see how the number of ground plane layers and gap size of via clearances affect power integrity. In a package with a through-hole via (a via penetrating the ground plane perpendicularly), while gigahertz frequency current is passing the via, electromagnetic wave leaks on ground planes, turns to be surface current which diffuses all over the planes repeating multiple reflection, and finally yields stored charges at via antipads. It causes waveform distortion as well as vertical level shift. It is proved that for high speed digital signal transmission, the less number of ground planes and the broader gap of clearances can reduce insertion loss and unwanted resonance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Signal-Integrity / Power-Integrity / VLSI-Package / Flip-Chip mounting / Multi-Layer PCB / Build-Up PCB |
| Paper # | CPM2005-96,ICD2005-106 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2005/9/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Assistant | |
| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The study of the high frequency electrical characteristics in high-speed digital device mounting : The Characteristic of high speed transmission of Flip-Chip Mounting |
| Sub Title (in English) | |
| Keyword(1) | Signal-Integrity |
| Keyword(2) | Power-Integrity |
| Keyword(3) | VLSI-Package |
| Keyword(4) | Flip-Chip mounting |
| Keyword(5) | Multi-Layer PCB |
| Keyword(6) | Build-Up PCB |
| 1st Author's Name | Chihiro Ueda |
| 1st Author's Affiliation | AET JAPAN, INC() |
| Date | 2005-09-09 |
| Paper # | CPM2005-96,ICD2005-106 |
| Volume (vol) | vol.105 |
| Number (no) | 266 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |