| Presentation | 2005-07-27 Automatic Logic Synthesis Scheme and Tool Implementation for Single-Flux-Quantum Circuits Yoshio KAMEDA, Shinichi YOROZU, Yoshihito HASHIMOTO, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Single-flux-quantum (SFQ) logic circuits provide us a faster operation with low power consumption using Josephson junctions as switching device. In the top-down SFQ circuit design flow, we have already developed a place-and-route tool that covers the back-end circuit design. In this paper, we present an automatic SFQ logic synthesis method that covers the front-end circuit design. The logic synthesis is a process that generates a gate-level logic circuit from a functional specification written in hardware description languages, such as Verilog-HDL and VHDL. Differences in between level-sensitive CMOS logic and pulse-driven SFQ logic have prevented a direct application of existing CMOS logic synthesis methods to the synthesis of SFQ logic circuits. The automatic logic synthesis scheme we present here consists of two procedures. After we generate a level-sensitive intermediate circuit by using a commercially available CMOS logic synthesis tool, we execute a post-process that converts the intermediate circuit into a pulse-driven SFQ circuit. We implemented the synthesis tool that can be linked to the automatic place-and-route tool we previously developed. These design tools enable a seamless automatic SFQ circuit design. Using the automatic synthesis tool, we generated adders and ALUs of various bit widths. For example, it took only two and half minutes to synthesize a 64-bit SFQ ALU with 16 operations. The generated SFQ circuit has 18000 logic gates. This result shows the effectiveness of our synthesis method and tool for large-scale SFQ logic circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Single-Flux-Quantum (SFQ) circuit / logic synthesis / pulse-driven logic / electronic design automation / hardware description language |
| Paper # | SCE2005-17 |
| Date of Issue |
| Conference Information | |
| Committee | SCE |
|---|---|
| Conference Date | 2005/7/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Automatic Logic Synthesis Scheme and Tool Implementation for Single-Flux-Quantum Circuits |
| Sub Title (in English) | |
| Keyword(1) | Single-Flux-Quantum (SFQ) circuit |
| Keyword(2) | logic synthesis |
| Keyword(3) | pulse-driven logic |
| Keyword(4) | electronic design automation |
| Keyword(5) | hardware description language |
| 1st Author's Name | Yoshio KAMEDA |
| 1st Author's Affiliation | ISTEC/SRL() |
| 2nd Author's Name | Shinichi YOROZU |
| 2nd Author's Affiliation | ISTEC/SRL |
| 3rd Author's Name | Yoshihito HASHIMOTO |
| 3rd Author's Affiliation | ISTEC/SRL |
| Date | 2005-07-27 |
| Paper # | SCE2005-17 |
| Volume (vol) | vol.105 |
| Number (no) | 210 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |