Presentation | 2005/7/29 Fault-tolerant Processor System by LUT and Microprogram Yousuke NAKAMURA, Kei HIRAKI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We study how to repair permanent faults in processors when it is difficult to exchange for spare ones. To resolve this problem, duplication method and substitution method is prepared, while we propose reconstruction method. In this paper, we discuss about fault detection system and restoring flow in reconstruction system. We made fault-detection logic circuit for binary counter. This fault detection system require 4 times re-configuration for binary counter. The numuber is so small. This method is realized to be useful for small circuit. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Dependability / Fault-Tolerant / Permanent Fault |
Paper # | DC2005-17 |
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Committee | DC |
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Conference Date | 2005/7/29(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Fault-tolerant Processor System by LUT and Microprogram |
Sub Title (in English) | |
Keyword(1) | Dependability |
Keyword(2) | Fault-Tolerant |
Keyword(3) | Permanent Fault |
1st Author's Name | Yousuke NAKAMURA |
1st Author's Affiliation | The University of Tokyo, Graduate School of Information Science and Technology() |
2nd Author's Name | Kei HIRAKI |
2nd Author's Affiliation | The University of Tokyo, Graduate School of Information Science and Technology |
Date | 2005/7/29 |
Paper # | DC2005-17 |
Volume (vol) | vol.105 |
Number (no) | 227 |
Page | pp.pp.- |
#Pages | 6 |
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