Presentation 2002/3/7
High performance Packet Assembly method Considering an Internet Traffic Analysis
Yoshiki URANISHI, Toshikatu KANDA, Kazunori SHIMAMURA,
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Abstract(in English) Due to the increasing amount of the Internet traffic, not only link capacity but also high-speed routers are required. In this paper, more than one of same IP destination packets are assembled to a packet at Edge Router of Core Network. These packets are transmitted efficiently on Core Network Router. We call this method "Packet Assembly". This method must make the packets concatenated during a fixed period at Edge Router. This period is relevant to both the efficiency of packet assembly and packet delay. In this paper, we explored this transfer method considering the real traffic characteristic.
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Keyword(in English) Packet Assembly / processor load / Internet Traffic / Edge router / flow
Paper # NS2001-237
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Committee NS
Conference Date 2002/3/7(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) High performance Packet Assembly method Considering an Internet Traffic Analysis
Sub Title (in English)
Keyword(1) Packet Assembly
Keyword(2) processor load
Keyword(3) Internet Traffic
Keyword(4) Edge router
Keyword(5) flow
1st Author's Name Yoshiki URANISHI
1st Author's Affiliation Department of Engineering,graduate School of Engineering, Kochi University of Technology()
2nd Author's Name Toshikatu KANDA
2nd Author's Affiliation Kochi Research Center, Telecommunications Advancement Organization of Japan A359 Kochi University of Technology
3rd Author's Name Kazunori SHIMAMURA
3rd Author's Affiliation Department of Engineering,graduate School of Engineering, Kochi University of Technology:Kochi Research Center, Telecommunications Advancement Organization of Japan A359 Kochi University of Technology
Date 2002/3/7
Paper # NS2001-237
Volume (vol) vol.101
Number (no) 714
Page pp.pp.-
#Pages 6
Date of Issue