| Presentation | 2005/3/10 Hardware Cryptography-Embedded Multimedia Mobile Processor Masaaki Fukase, Youichi Sato, Yoshiki Nakamura, Ryo Akaoka, Tomoaki Sato, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Internet owes its outstanding expansion in recent years to the development of handheld multimedia devices. The performable features of these devices have mainly relied on software approaches. However, this obviously contradicts power conscious design. The hardware system of a single VLSI processor is indispensable to fulfill demands for the power conscious high speed cryptography of large quantity of multimedia data. Setting up the drastic throughput of 1GIPS (10^9 instructions/sec) and 1-W power dissipation, we have exploited the architecture of a hardware security-embedded multimedia mobile processor named HSgorilla by sophisticatedly unifying up-to-date processor techniques. This paper focuses on HSgorilla's aspects, application, and design approach for one of processor cores, HSgorilla035, by using 0.35-μm CMOS standard cell technology. Although the throughput is 0.6GIPS, power consumption is 740mW. Thus, we can afford to further enhance the throughput. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RAC / RNG / FIFO / SMT / VLIW / Data cache |
| Paper # | SIS2004-61 |
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| Conference Information | |
| Committee | SIS |
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| Conference Date | 2005/3/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Smart Info-Media Systems (SIS) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Cryptography-Embedded Multimedia Mobile Processor |
| Sub Title (in English) | |
| Keyword(1) | RAC |
| Keyword(2) | RNG |
| Keyword(3) | FIFO |
| Keyword(4) | SMT |
| Keyword(5) | VLIW |
| Keyword(6) | Data cache |
| 1st Author's Name | Masaaki Fukase |
| 1st Author's Affiliation | Department of Electronics and Information Systems Engineering, Hirosaki University() |
| 2nd Author's Name | Youichi Sato |
| 2nd Author's Affiliation | Department of Electronics and Information Systems Engineering, Hirosaki University |
| 3rd Author's Name | Yoshiki Nakamura |
| 3rd Author's Affiliation | Department of Electronics and Information Systems Engineering, Hirosaki University |
| 4th Author's Name | Ryo Akaoka |
| 4th Author's Affiliation | Department of Electronics and Information Systems Engineering, Hirosaki University |
| 5th Author's Name | Tomoaki Sato |
| 5th Author's Affiliation | Sapporo Gakuin University |
| Date | 2005/3/10 |
| Paper # | SIS2004-61 |
| Volume (vol) | vol.104 |
| Number (no) | 735 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |