Presentation 2004-10-21
Noise and process variation-tolerant multi-ported register file using 130 nm technology
Yuuichirou Ikeda, Masaya Sumita,
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Abstract(in English) We have developed a 32-bit, 64-word 9-read, 7-write ported register file for a processor based on 130 nm process technology. This register file has several circuits for improving noise and process variation tolerance, such as self-timing control circuits and crosstalk reduction circuits. Body bias voltage control can also be employed. These circuits and techniques confer tolerance to noise and process variation, allowing the register file to be operated over a wide voltage range from 0.6 V to 2.2 V.
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Keyword(in English) multi-media processor / multi-ported / register file / process variation / signal noise
Paper # SIP2004-87,ICD2004-119,IE2004-63
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Conference Information
Committee SIP
Conference Date 2004/10/14(1days)
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Registration To Signal Processing (SIP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Noise and process variation-tolerant multi-ported register file using 130 nm technology
Sub Title (in English)
Keyword(1) multi-media processor
Keyword(2) multi-ported
Keyword(3) register file
Keyword(4) process variation
Keyword(5) signal noise
1st Author's Name Yuuichirou Ikeda
1st Author's Affiliation Matsushita Electric Industrial Co., Ltd.()
2nd Author's Name Masaya Sumita
2nd Author's Affiliation Matsushita Electric Industrial Co., Ltd.
Date 2004-10-21
Paper # SIP2004-87,ICD2004-119,IE2004-63
Volume (vol) vol.104
Number (no) 363
Page pp.pp.-
#Pages 6
Date of Issue