Presentation 2003/8/26
Buffer Management based on a Parallel and Pipeline Mechanism to Support 128×128 Photonic Packet Switches with 40Gbps Ports
Hiroaki HARAI, Masayuki MURATA,
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Abstract(in English) We investigate a high-speed buffer management mechanism for output-butffered photonic packet switches. We propose a parallel and pipeline mechanism on multi-processing architecture for this purpose. The machanism provides N times faster processing than an existing O(N) mechanism does, where N is the number of ports. Through hardware simulation after place and route operation, we confirm feasibility of an FPGA-based buffer management hardware for 8×8 photonic packet switches with 40Gbps ports, which is capable of asynchronously arriving variable-size packets, of which minimum is 64byte. A support of 128×128 packet switch with 40Gbps ports is also feasible by using our mechanism and a latest FPGA technology.
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Keyword(in English) Photonic packet switch / Output buffer / Parallel and pipeline processing / Asynchronous variable-size packets / Field programmable gate array
Paper # PN2003-7
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Conference Date 2003/8/26(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Buffer Management based on a Parallel and Pipeline Mechanism to Support 128×128 Photonic Packet Switches with 40Gbps Ports
Sub Title (in English)
Keyword(1) Photonic packet switch
Keyword(2) Output buffer
Keyword(3) Parallel and pipeline processing
Keyword(4) Asynchronous variable-size packets
Keyword(5) Field programmable gate array
1st Author's Name Hiroaki HARAI
1st Author's Affiliation Communications Research Laboratory()
2nd Author's Name Masayuki MURATA
2nd Author's Affiliation Osaka University
Date 2003/8/26
Paper # PN2003-7
Volume (vol) vol.103
Number (no) 281
Page pp.pp.-
#Pages 6
Date of Issue