Presentation | 2004/11/20 Design of Inverse Function Delayed neuro chip with learing function Jun FUKUHARA, Shinya SUENAGA, Yoshihiro HAYAKAWA, Koji NAKAJIMA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Practical application of neural network requires hardware implementation. And in order to a good performance hardware, it should implement high ability neuron model. We know that our supposed Inverse Function Delayed (ID) model which shows negative resistance effect has the high ability in learning and optimized problems. Hence we implement ID neuron on LSI. Our circuit comprises 25 neurons and full connected network with a learning function. In this report, we describe mainly the HSPICE simulation result of this circuit. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | negative resistance / inverse function / DBM learning / analog circuit / CMOS |
Paper # | NLP2004-83,NC2004-99 |
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Committee | NC |
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Conference Date | 2004/11/20(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Neurocomputing (NC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Design of Inverse Function Delayed neuro chip with learing function |
Sub Title (in English) | |
Keyword(1) | negative resistance |
Keyword(2) | inverse function |
Keyword(3) | DBM learning |
Keyword(4) | analog circuit |
Keyword(5) | CMOS |
1st Author's Name | Jun FUKUHARA |
1st Author's Affiliation | Laboratory for Brainware/Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University() |
2nd Author's Name | Shinya SUENAGA |
2nd Author's Affiliation | / / |
3rd Author's Name | Yoshihiro HAYAKAWA |
3rd Author's Affiliation | |
4th Author's Name | Koji NAKAJIMA |
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Date | 2004/11/20 |
Paper # | NLP2004-83,NC2004-99 |
Volume (vol) | vol.104 |
Number (no) | 474 |
Page | pp.pp.- |
#Pages | 6 |
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