| Presentation | 2004/11/20 Spiking Neuron Circuit Using Single-Electron Tunneling Device with Fault-Tolerant Architecture Takahide OYA, Alexandre SCHMID, Tetsuya ASAI, Yusuf LEBLEBICI, Yoshihito AMEMIYA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, we present an inhibitory spiking neural network that uses single-electron circuit devices. Recently, the study of various nanodevices such like single-electron devices is developed furthermore. The device failure or signal noise, however, will be problems, when the nanodevices are fabricated. To solve these problems, we constructed the inhibitory competitive network that consists of a single-electron circuit with the fault-tolerant architecture. We confirmed the operations of the proposed circuits by using computer simulation. These simulation results show the proposed circuit promises to overcome the device failure or the signal noise. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Spiking Neuron Circuit / Inhibitory Competitive Network / Single-Electron Circuit / Fault-Tolerant Architecture |
| Paper # | NLP2004-77,NC2004-93 |
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| Conference Information | |
| Committee | NC |
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| Conference Date | 2004/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Neurocomputing (NC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Spiking Neuron Circuit Using Single-Electron Tunneling Device with Fault-Tolerant Architecture |
| Sub Title (in English) | |
| Keyword(1) | Spiking Neuron Circuit |
| Keyword(2) | Inhibitory Competitive Network |
| Keyword(3) | Single-Electron Circuit |
| Keyword(4) | Fault-Tolerant Architecture |
| 1st Author's Name | Takahide OYA |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, Hokkaido University() |
| 2nd Author's Name | Alexandre SCHMID |
| 2nd Author's Affiliation | Microelectronic Systems Laboratory, Swiss Federal Institute of Technology (EPFL) |
| 3rd Author's Name | Tetsuya ASAI |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, Hokkaido University |
| 4th Author's Name | Yusuf LEBLEBICI |
| 4th Author's Affiliation | Microelectronic Systems Laboratory, Swiss Federal Institute of Technology (EPFL) |
| 5th Author's Name | Yoshihito AMEMIYA |
| 5th Author's Affiliation | Graduate School of Information Science and Technology, Hokkaido University |
| Date | 2004/11/20 |
| Paper # | NLP2004-77,NC2004-93 |
| Volume (vol) | vol.104 |
| Number (no) | 474 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |