| Presentation | 2005-03-17 Integrated Interleaving Method with Sum-Product Algorithm Hironori KATO, Hiroshi KAMABE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An Integrated interleaving is a coding scheme which enhances the error correcting capability of a system consisting of different ECCs. We use this method with high dimensional parity codes and array-LDPC codes as its constituent codes. We show that we can employ the sum-product algorithm with appropriate likelihood functions in this scheme and analyze the performance of these coding schemes. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Linear codes / LDPC codes / Magnetic recording / Interleaving |
| Paper # | IT2004-64,ISEC2004-120,WBS2004-179 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2005/3/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Integrated Interleaving Method with Sum-Product Algorithm |
| Sub Title (in English) | |
| Keyword(1) | Linear codes |
| Keyword(2) | LDPC codes |
| Keyword(3) | Magnetic recording |
| Keyword(4) | Interleaving |
| 1st Author's Name | Hironori KATO |
| 1st Author's Affiliation | Graduate school of Engineering Gifu university() |
| 2nd Author's Name | Hiroshi KAMABE |
| 2nd Author's Affiliation | Graduate school of Engineering Gifu university |
| Date | 2005-03-17 |
| Paper # | IT2004-64,ISEC2004-120,WBS2004-179 |
| Volume (vol) | vol.104 |
| Number (no) | 731 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |