Presentation 2005/1/14
Nano-wiring Process based on Nano-insulation Bed
Mikinori Suzuki, Shinzo Morita,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Processes for nano-wiring circuit (inter-connection technology) with nano-meter level dimension were proposed. Nano-insulation beds as barrier free quantum device evaluation circuit have been presented, therefore nano-wiring circuit will be fabricated with using the bed system. 100nmL&S structure of electron beam resist with trench on n-type Si wafer was fabricated and Au was tried to fill in the trench by electro-plating using ethanol NaAuCl_4 was solved at 0.5atom%. Au was successfully plated on Si wafer through the 100 nm width patterns. Ultra fine wiring patterns of Au plating will be realized with using nano-insulating beds along the conductive lines.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) nano-insulation bed / nano-wiring / NaAuCl_4 / electro-plating
Paper # OME2004-116
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Conference Information
Committee OME
Conference Date 2005/1/14(1days)
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Paper Information
Registration To Organic Material Electronics (OME)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Nano-wiring Process based on Nano-insulation Bed
Sub Title (in English)
Keyword(1) nano-insulation bed
Keyword(2) nano-wiring
Keyword(3) NaAuCl_4
Keyword(4) electro-plating
1st Author's Name Mikinori Suzuki
1st Author's Affiliation Department of Electronic Information System, Graduate School of Engineering Nagoya University()
2nd Author's Name Shinzo Morita
2nd Author's Affiliation Department of Electronic Information System, Graduate School of Engineering Nagoya University
Date 2005/1/14
Paper # OME2004-116
Volume (vol) vol.104
Number (no) 578
Page pp.pp.-
#Pages 4
Date of Issue