Presentation	2005/5/12 Design and Simulation of low power consumption of multiplier by using the partial constant Syuuichi Sugimoto, Akihiro Endou, Masayoshi Tachibana,
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Abstract(in English)	In this paper, we consider a method of designing low power consumption multiplier by using partial constant. The main idea of the method is to remove redundant part of multiplier by fixing the digit that does not change with always 0. Here, we simulate to the partial constant multiplier. Simulation results show that the method can do low power consumption.
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Keyword(in English)	Partial constant / Multiplier / Low power consumption
Paper #	VLD2005-4
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Committee	VLD
Conference Date	2005/5/12(1days)
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Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Design and Simulation of low power consumption of multiplier by using the partial constant
Sub Title (in English)
Keyword(1)	Partial constant
Keyword(2)	Multiplier
Keyword(3)	Low power consumption
1st Author's Name	Syuuichi Sugimoto
1st Author's Affiliation	Electronic and Photonic Systems Engineering Course, Kochi University of Technology()
2nd Author's Name	Akihiro Endou
2nd Author's Affiliation	Electronic and Photonic Systems Engineering Course, Kochi University of Technology
3rd Author's Name	Masayoshi Tachibana
3rd Author's Affiliation	Electronic and Photonic Systems Engineering Course, Kochi University of Technology
Date	2005/5/12
Paper #	VLD2005-4
Volume (vol)	vol.105
Number (no)	57
Page	pp.pp.-
#Pages	5
Date of Issue