Presentation 2005/3/4
Adaptive Way-Predicting Cache for Low Power Consumption
Hidekazu TANAKA, Koji INOUE, Vasily G. Moshnyaga,
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Abstract(in English) We have proposed a novel cache architecture for low power consumption, called "Adaptive Way-Predicting Cache (AWP cache)". The AWP cache has three different operation modes, and dynamically switches the modes according to the behavior of the memory reference when program is executed. To analyze the effectiveness of the AWP cache, we evaluate the energy consumption and the performance based on the simulation and the circuit design. We have evaluated the AWP cache using many benchmarks. As the results, it is observed that the performance improvement achieved by the AWP cache is about 25% in the best case, compared to the WP cache. And it is observed that the energy improvement achieved by the AWP cache is about 60% in the best case, compared to the WP cache.
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Keyword(in English) low power consumption / cache / way / prediction / dynamic switching
Paper # VLD2004-139,ICD2004-235
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Committee VLD
Conference Date 2005/3/4(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Adaptive Way-Predicting Cache for Low Power Consumption
Sub Title (in English)
Keyword(1) low power consumption
Keyword(2) cache
Keyword(3) way
Keyword(4) prediction
Keyword(5) dynamic switching
1st Author's Name Hidekazu TANAKA
1st Author's Affiliation Department of Electronics Engineering, Fukuoka University()
2nd Author's Name Koji INOUE
2nd Author's Affiliation Department of Informatics, Kyushu University
3rd Author's Name Vasily G. Moshnyaga
3rd Author's Affiliation Department of Electronics Engineering and Computer Science, Fukuoka University
Date 2005/3/4
Paper # VLD2004-139,ICD2004-235
Volume (vol) vol.104
Number (no) 709
Page pp.pp.-
#Pages 6
Date of Issue