| Presentation | 2005/3/4 Power Reduction Technique of Subthreshold CMOS Digital Circuits Using PTAT Reference Voltage Generator Jun MIYAMOTO, Shinsaku SHIMIZU, Tsukasa IDA, Toshimasa MATSUOKA, Kenji TANIGUCHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In CMOS digital circuit operating in weak inversion, power consumption increases along with the rise of temperature. In this study, the power-supply voltage of the ring oscillator operating in weak inversion is changed using PTAT reference voltage generator and the power consumption at the high temperature has been reduced with operation speed kept. In addition, it was shown to be able to achieve power reduction using the proposed technique even in a large-scale digital circuit system. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | weak inversion / Proportional-to-Absolute Temperature(PTAT) / low power / digital circuit |
| Paper # | VLD2004-138,ICD2004-234 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2005/3/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power Reduction Technique of Subthreshold CMOS Digital Circuits Using PTAT Reference Voltage Generator |
| Sub Title (in English) | |
| Keyword(1) | weak inversion |
| Keyword(2) | Proportional-to-Absolute Temperature(PTAT) |
| Keyword(3) | low power |
| Keyword(4) | digital circuit |
| 1st Author's Name | Jun MIYAMOTO |
| 1st Author's Affiliation | Department of Electronics and Information Systems, Osaka University() |
| 2nd Author's Name | Shinsaku SHIMIZU |
| 2nd Author's Affiliation | Department of Electronics and Information Systems, Osaka University |
| 3rd Author's Name | Tsukasa IDA |
| 3rd Author's Affiliation | Department of Electronics and Information Systems, Osaka University |
| 4th Author's Name | Toshimasa MATSUOKA |
| 4th Author's Affiliation | Department of Electronics and Information Systems, Osaka University |
| 5th Author's Name | Kenji TANIGUCHI |
| 5th Author's Affiliation | Department of Electronics and Information Systems, Osaka University |
| Date | 2005/3/4 |
| Paper # | VLD2004-138,ICD2004-234 |
| Volume (vol) | vol.104 |
| Number (no) | 709 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |