Presentation | 2005/3/3 Fast Modular Multiplication by Processing the Multiplier from Both Sides in Parallel Marcelo E. KAIHARA, Naofumi TAKAGI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We propose a fast method for computing modular multiplication, in which the calculation is performed over newly defined Montgomery images. The Montgomery multiplication is newly defined so that it can be efficiently computed by using the classical shift-and-add algorithm and the Montgomery algorithm in parallel. This method enables to accelerate modular multiplication up to twice the speed of existing algorithms. Transformations between the binary representation and the newly defined Montgomery image can be performed in half the time than that required when conventional Montgomery representation is used. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | modular arithmetic / modular multiplication / Montgomery algorithm / shift-and-add algorithm |
Paper # | VLD2004-124,ICD2004-220 |
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Committee | VLD |
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Conference Date | 2005/3/3(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | VLSI Design Technologies (VLD) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Fast Modular Multiplication by Processing the Multiplier from Both Sides in Parallel |
Sub Title (in English) | |
Keyword(1) | modular arithmetic |
Keyword(2) | modular multiplication |
Keyword(3) | Montgomery algorithm |
Keyword(4) | shift-and-add algorithm |
1st Author's Name | Marcelo E. KAIHARA |
1st Author's Affiliation | Department of Information Engineering, Nagoya University() |
2nd Author's Name | Naofumi TAKAGI |
2nd Author's Affiliation | Department of Information Engineering, Nagoya University |
Date | 2005/3/3 |
Paper # | VLD2004-124,ICD2004-220 |
Volume (vol) | vol.104 |
Number (no) | 708 |
Page | pp.pp.- |
#Pages | 4 |
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