| Presentation | 2005-01-26 Extraction of Instruction Latency from Cycle-True Processor Models Yusuke HIRAOKA, Nagisa ISHIURA, Masaharu IMAI, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this parer, we present a method of extracting instruction latency considering forwarding from processor specification of "ASIP-Meister." The forwarding is assumed to be specified in cycle-accurate behavior description of each instruction using forwarding units. Based on the connectivities between the instructions and the forwarding units, we define the validity and the completeness of the forwarding, and formulate the instruction latency under the existence of valid and complete forwarding. We also show a method of reducing the data amount for recording instruction latency based on a classification of the register reads and writes of the instructions. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | retargetable compilers / instruction latency / forwarding / scheduling / ASIP-Meister |
| Paper # | VLD2004-119,CPSY2004-85 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 2005/1/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Extraction of Instruction Latency from Cycle-True Processor Models |
| Sub Title (in English) | |
| Keyword(1) | retargetable compilers |
| Keyword(2) | instruction latency |
| Keyword(3) | forwarding |
| Keyword(4) | scheduling |
| Keyword(5) | ASIP-Meister |
| 1st Author's Name | Yusuke HIRAOKA |
| 1st Author's Affiliation | Graduate School of Science, Kwansei Gakuin University() |
| 2nd Author's Name | Nagisa ISHIURA |
| 2nd Author's Affiliation | School of Science and Technology, Kwansei Gakuin University |
| 3rd Author's Name | Masaharu IMAI |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| Date | 2005-01-26 |
| Paper # | VLD2004-119,CPSY2004-85 |
| Volume (vol) | vol.104 |
| Number (no) | 590 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |