Presentation	2005-01-25 Verification IP and Assertion for IP-Reuse promotion : Verification IP and the related activities in STARC Masanori Imai,
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Abstract(in English)	Growing complexity of SoC's and reducing life cycle time of electronic products both are demanding higher design productivity. IP reuse is an absolute must for its solution. Consequently, the growing number of IP cores tend to be integrated into a single chip to improve the productivity. As well known, integrated IP cores include 3^ party IP cores besides dedicated IP ones. The 3^ party IP cores are sometimes said to be problematic in functional quality, which is one of the main roadblocks that disturb IP reuse promotion. Therefore, to ease IP reuse, we need to close design-verification gap in advance by IP quality enhancements and efficient verification methodologies like as the assertion technology. We are developing IP related standards leading to attaining our goals. A guideline for verification IP's including assertion checkers is one of such standards. Those activities in STARC are outlined.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Assertion / Verification / Verification IP / Testbench / HVL / IP quality / deliverables
Paper #	VLD2004-103,CPSY2004-69
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Conference Information
Committee	VLD
Conference Date	2005/1/18(1days)
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Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Verification IP and Assertion for IP-Reuse promotion : Verification IP and the related activities in STARC
Sub Title (in English)
Keyword(1)	Assertion
Keyword(2)	Verification
Keyword(3)	Verification IP
Keyword(4)	Testbench
Keyword(5)	HVL
Keyword(6)	IP quality
Keyword(7)	deliverables
1st Author's Name	Masanori Imai
1st Author's Affiliation	IP Reuse Group, Design Technology Development Dept. STARC()
Date	2005-01-25
Paper #	VLD2004-103,CPSY2004-69
Volume (vol)	vol.104
Number (no)	589
Page	pp.pp.-
#Pages	4
Date of Issue