| Presentation | 2005-01-25 Reconfigurable 1-bit processor array with reduced wiring area Nobuo NAKAI, Masaki NAKANISHI, Shigeru YAMASHITA, Katsumasa WATANABE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Semiconductor makers have a problem of how to reduce the production cost. Because of the increasing gates to implement and shortening production cycle, production cost is increasing. One of the way to solve this problem is to use of reconfigurable hardwares. Although reconfigurable hardwares seemed to be useful, they have some disadvantages. As a result, a system using software or ASIC costs lower than reconfigurable hardware in many cases. In this paper we propose an efficient architecture of reconfigurable hardware with low cost. The proposed architecture has the following features; It has high routability but wiring area is reduced, and number of processor elements can be increase easily. We mapped DCT circuit to proposed architecture and run. We also show some experimental results. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable computing / coarse-grain architecture / bit-serial data path / wiring resource |
| Paper # | VLD2004-98,CPSY2004-64 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2005/1/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reconfigurable 1-bit processor array with reduced wiring area |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable computing |
| Keyword(2) | coarse-grain architecture |
| Keyword(3) | bit-serial data path |
| Keyword(4) | wiring resource |
| 1st Author's Name | Nobuo NAKAI |
| 1st Author's Affiliation | Nara Institute of Science and Technology() |
| 2nd Author's Name | Masaki NAKANISHI |
| 2nd Author's Affiliation | Nara Institute of Science and Technology |
| 3rd Author's Name | Shigeru YAMASHITA |
| 3rd Author's Affiliation | Nara Institute of Science and Technology |
| 4th Author's Name | Katsumasa WATANABE |
| 4th Author's Affiliation | Nara Institute of Science and Technology |
| Date | 2005-01-25 |
| Paper # | VLD2004-98,CPSY2004-64 |
| Volume (vol) | vol.104 |
| Number (no) | 589 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |