Presentation 2004/11/24
Rapid Instruction Set Evaluation for Application Specific Processor
Masayuki MASUDA, Kazuhito ITO,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) The selection of instruction set of a processor greatly influences the processor hardware and execution of software in speed, area, and power. Evaluation of instruction set is an important task in designing a processor specific to a given application. In this paper, a technique to rapidly and precisely evaluate instruction sets for the given application is proposed. The results show the proposed technique efficiently evaluate instruction sets for assumed processor hardware.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Application-specific processor / Processor design / Instruction-set evaluation / DAG covering / Branch and bound
Paper # VLD2004-51,ICD2004-137,DC2004-37
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Conference Information
Committee VLD
Conference Date 2004/11/24(1days)
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Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Rapid Instruction Set Evaluation for Application Specific Processor
Sub Title (in English)
Keyword(1) Application-specific processor
Keyword(2) Processor design
Keyword(3) Instruction-set evaluation
Keyword(4) DAG covering
Keyword(5) Branch and bound
1st Author's Name Masayuki MASUDA
1st Author's Affiliation Department of Electrical and Electronic Systems, Saitama University()
2nd Author's Name Kazuhito ITO
2nd Author's Affiliation Department of Electrical and Electronic Systems, Saitama University
Date 2004/11/24
Paper # VLD2004-51,ICD2004-137,DC2004-37
Volume (vol) vol.104
Number (no) 477
Page pp.pp.-
#Pages 6
Date of Issue