| Presentation | 2005-05-26 A Low-power Systolic Array Architecture for Block-matching Motion Estimation Junichi MIYAKOSHI, Yuichiro MURACHI, Koji HAMANO, Tetsuro MATSUNO, Masayuki MIYAMA, Masahiko YOSHIMOTO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This Paper describes a low-power systolic array architecture for a block-matching motion estimation for high-resolution video applications. The architecture features to reduce both computing cycles and memory accesses by using a ring-connected processing element array. Furthermore, the architecture allows various summation schemes for absolute difference. For that reason, it is applicable to various video coding mode such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced a design of a MPEG2 MP@HL motion estimator VLSI, the power consumption of the processor is reduced by 45%-73% in comparison to cases with conventional architectures for motion estimation. A motion estimation processor using the architecture is applicable to portable high-resolution video systems. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | HDTV / MPEG2 / Motion Estimation / Low Power / Mobile Video System / Signal Processing |
| Paper # | ICD2005-20 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2005/5/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low-power Systolic Array Architecture for Block-matching Motion Estimation |
| Sub Title (in English) | |
| Keyword(1) | HDTV |
| Keyword(2) | MPEG2 |
| Keyword(3) | Motion Estimation |
| Keyword(4) | Low Power |
| Keyword(5) | Mobile Video System |
| Keyword(6) | Signal Processing |
| 1st Author's Name | Junichi MIYAKOSHI |
| 1st Author's Affiliation | Graduate School of Natural Science and Technology, Kanazawa University() |
| 2nd Author's Name | Yuichiro MURACHI |
| 2nd Author's Affiliation | Graduate School of Natural Science and Technology, Kanazawa University |
| 3rd Author's Name | Koji HAMANO |
| 3rd Author's Affiliation | Graduate School of Natural Science and Technology, Kanazawa University |
| 4th Author's Name | Tetsuro MATSUNO |
| 4th Author's Affiliation | Graduate School of Natural Science and Technology, Kanazawa University |
| 5th Author's Name | Masayuki MIYAMA |
| 5th Author's Affiliation | Graduate School of Natural Science and Technology, Kanazawa University |
| 6th Author's Name | Masahiko YOSHIMOTO |
| 6th Author's Affiliation | Graduate School of Natural Science and Technology, Kanazawa University |
| Date | 2005-05-26 |
| Paper # | ICD2005-20 |
| Volume (vol) | vol.105 |
| Number (no) | 95 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |