| Presentation | 2005-04-14 4Gb Multilevel AG-AND Flash Memory with 10MB/s Programming Throughput Hideaki Kurata, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume, Kazuki Homma, Kenji Kozakai, Satoshi Noda, Teruhiko Ito, Masahiro Shimizu, Yoshihiro Ikeda, Osamu Tsuchiya, Kazunori Furusawa, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We fabricated a 4Gb multilevel AG-AND flash memory using 90nm CMOS technology. By using an inversion-layer local-bitline technology, the bit-line pitch is reduced to 2 F, resulting in a 126 mm^2 chip size and a 0.0162μm^2/bit cell size. To achieve 2-bits/cell, we have to precisely control the large resistance of the inversion-layer bit-line. In reading operations, two compensation methods, the address compensation and temperature compensation methods, were applied. In programming operations, charge-sharing scheme suppresses the difference in programming speeds along the string and self-boosting scheme reduces the time overhead of pre-charging bitlines. With these two schemes, a high programming throughput of 10 MB/s is achieved, even in multilevel flash memory. We have also provided a cache-read function to achieve a high access throughput of 22 MB/s. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Flash Memory / Multi-Level Technology / AG-AND / Inversion-Layer |
| Paper # | ICD2005-11 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2005/4/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 4Gb Multilevel AG-AND Flash Memory with 10MB/s Programming Throughput |
| Sub Title (in English) | |
| Keyword(1) | Flash Memory |
| Keyword(2) | Multi-Level Technology |
| Keyword(3) | AG-AND |
| Keyword(4) | Inversion-Layer |
| 1st Author's Name | Hideaki Kurata |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
| 2nd Author's Name | Yoshitaka Sasago |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 3rd Author's Name | Kazuo Otsuga |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 4th Author's Name | Tsuyoshi Arigane |
| 4th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 5th Author's Name | Tetsufumi Kawamura |
| 5th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 6th Author's Name | Takashi Kobayashi |
| 6th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 7th Author's Name | Hitoshi Kume |
| 7th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 8th Author's Name | Kazuki Homma |
| 8th Author's Affiliation | Renesas Technology Corp. |
| 9th Author's Name | Kenji Kozakai |
| 9th Author's Affiliation | Renesas Technology Corp. |
| 10th Author's Name | Satoshi Noda |
| 10th Author's Affiliation | Renesas Technology Corp. |
| 11th Author's Name | Teruhiko Ito |
| 11th Author's Affiliation | Renesas Technology Corp. |
| 12th Author's Name | Masahiro Shimizu |
| 12th Author's Affiliation | Renesas Technology Corp. |
| 13th Author's Name | Yoshihiro Ikeda |
| 13th Author's Affiliation | Renesas Technology Corp. |
| 14th Author's Name | Osamu Tsuchiya |
| 14th Author's Affiliation | Renesas Technology Corp. |
| 15th Author's Name | Kazunori Furusawa |
| 15th Author's Affiliation | Renesas Technology Corp. |
| Date | 2005-04-14 |
| Paper # | ICD2005-11 |
| Volume (vol) | vol.105 |
| Number (no) | 1 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |