| Presentation | 2005-04-14 Statistical Integration in Multigigabit DRAM Design Tomonori Sekiguchi, Satoru Akiyama, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Concordant memory-array design incorporates device fluctuations statistically into signal-to-noise ratio analysis in DRAM. In this design, the effective signal voltage of all cells in a chip is calculated and failed bit count of the chip is estimated. The proposed technique gives us a quantitative evaluation of the memory array design, and analysis of the failed bit is also available. For a case-study, 1.4 V array operation of 100 nm - 1 Gb DRAM is assured. Calculated dependence of failed bit count on the array voltage is in good agreement with experimental results of the 512 Mbit DRAM chip. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Memory array design / fluctuation in device parameters / technology scaling / Monte-Carlo simulation |
| Paper # | ICD2005-8 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2005/4/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Statistical Integration in Multigigabit DRAM Design |
| Sub Title (in English) | |
| Keyword(1) | Memory array design |
| Keyword(2) | fluctuation in device parameters |
| Keyword(3) | technology scaling |
| Keyword(4) | Monte-Carlo simulation |
| 1st Author's Name | Tomonori Sekiguchi |
| 1st Author's Affiliation | Hitachi, Ltd., Central Research Laboratory() |
| 2nd Author's Name | Satoru Akiyama |
| 2nd Author's Affiliation | Hitachi, Ltd., Central Research Laboratory |
| 3rd Author's Name | Kazuhiko Kajigaya |
| 3rd Author's Affiliation | Elpida Memory Inc. |
| 4th Author's Name | Satoru Hanzawa |
| 4th Author's Affiliation | Hitachi, Ltd., Central Research Laboratory |
| 5th Author's Name | Riichiro Takemura |
| 5th Author's Affiliation | Hitachi, Ltd., Central Research Laboratory |
| 6th Author's Name | Takayuki Kawahara |
| 6th Author's Affiliation | Hitachi, Ltd., Central Research Laboratory |
| Date | 2005-04-14 |
| Paper # | ICD2005-8 |
| Volume (vol) | vol.105 |
| Number (no) | 1 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |