| Presentation | 2005/3/4 Implementation and Evaluation of Partial-Parallel LDPC Decoder Improving Belief Propagation based on Sum-Product Algorithm Kazunori SHIMIZU, Tatsuyuki ISHIKAWA, Nozomu TOGAWA, Takeshi IKENAGA, Satoshi GOTO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a partial-parallel LDPC decoder improving belief propagation based on sum-product algorithm. Our proposed partial-parallel LDPC decoder processes column operations for bit nodes in conjunction with row operations for check nodes. Bit functional unit with pipeline architecture in our LDPC decoder allows us to process column operations for every bit node connected to each of check nodes which are processed by row operations in parallel. Thus, our proposed LDPC decoder increases the number of belief propagations in the sum-product algorithm. We implemented the proposed partial-parallel LDPC decoder on a FPGA, and simulated its decoding performance. Practical simulation shows that our proposed partial-parallel LDPC decoder improves the number of iterations and bit error performance in the sum-product algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Low-Density Parity-Check(LDPC) codes / sum-product algorithm / partial-parallel LDPC decoder / FPGA |
| Paper # | VLD2004-149,ICD2004-245 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2005/3/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation and Evaluation of Partial-Parallel LDPC Decoder Improving Belief Propagation based on Sum-Product Algorithm |
| Sub Title (in English) | |
| Keyword(1) | Low-Density Parity-Check(LDPC) codes |
| Keyword(2) | sum-product algorithm |
| Keyword(3) | partial-parallel LDPC decoder |
| Keyword(4) | FPGA |
| 1st Author's Name | Kazunori SHIMIZU |
| 1st Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University() |
| 2nd Author's Name | Tatsuyuki ISHIKAWA |
| 2nd Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Information and Media Sciences, The University of Kitakyushu:Advanced Research Institute for Science and Engineering, Waseda University |
| 4th Author's Name | Takeshi IKENAGA |
| 4th Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University |
| 5th Author's Name | Satoshi GOTO |
| 5th Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University |
| Date | 2005/3/4 |
| Paper # | VLD2004-149,ICD2004-245 |
| Volume (vol) | vol.104 |
| Number (no) | 711 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |