| Presentation | 2005/3/4 A High-Speed Domino CMOS Full Adder Driven by a New Unified-BiCMOS Inverter with Resistor-Ratio Type Control Circuits Fumiaki Tamaki, Kei Matsuura, Toshiro Akino, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We proposed a new operation mode for a partially depleted CMOS inverter on SOI, and designed and simulated a hybrid lateral BJT-CMOS inverter circuit [1]. The scheme utilizes the gated lateral npn {pnp} BJT inherent of n {p}-channel MOSFET. Forward current is applied to the base terminal of the channel MOSFETs, with pull-up or pull-down MOSFET having normal substrates as current sources, where each drain terminal is connected to the corresponding base terminal of the inverter. We called this hybrid device as a new Unified(U)-BiCMOS inverter. A logic scheme is also proposed to control the gates of the pull-up or pull-down MOSFETs in switching states using output signals made from two normal substrate CMOS inverters with different resistance ratios. Here, we designed the U-BiCMOS inverter with the nearly same current capabilities for two complementary MOSFETs having the channel widths as Wp/Wn=2. In this paper, we investigate a circuit performance of the U-BiCMOS inverter with the nearly same current capabilities for two complementary BJTs. Circuit simulation using 0.35μm BSIM3v3 model parameters for MOSFETs and a current gain of β_F=100 for BJTs, the speed and energy consumption of Domino CMOS full adder driven by the U-BiCMOS inverter with Wp/Wn=1 are shown to be nearly 64% faster and 12% higher than those of 3-stage CMOS inverter designed on the basis of logical effort [2] for driving a load capacitance of 0.2361pF at Vdd=1.0V. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SOI / partially depleted / CMOS / BJT / MOSFET / BiCMOS / new Unified (U)-BiCMOS / logical effort |
| Paper # | VLD2004-147,ICD2004-243 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2005/3/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A High-Speed Domino CMOS Full Adder Driven by a New Unified-BiCMOS Inverter with Resistor-Ratio Type Control Circuits |
| Sub Title (in English) | |
| Keyword(1) | SOI |
| Keyword(2) | partially depleted |
| Keyword(3) | CMOS |
| Keyword(4) | BJT |
| Keyword(5) | MOSFET |
| Keyword(6) | BiCMOS |
| Keyword(7) | new Unified (U)-BiCMOS |
| Keyword(8) | logical effort |
| 1st Author's Name | Fumiaki Tamaki |
| 1st Author's Affiliation | Program in Electronic System and Information Engineering, The Graduate School of Biology-Oriented Science and Technology, Kinki University() |
| 2nd Author's Name | Kei Matsuura |
| 2nd Author's Affiliation | Program in Electronic System and Information Engineering, The Graduate School of Biology-Oriented Science and Technology, Kinki University |
| 3rd Author's Name | Toshiro Akino |
| 3rd Author's Affiliation | Program in Electronic System and Information Engineering, The Graduate School of Biology-Oriented Science and Technology, Kinki University |
| Date | 2005/3/4 |
| Paper # | VLD2004-147,ICD2004-243 |
| Volume (vol) | vol.104 |
| Number (no) | 711 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |