Presentation 2005/3/4
An Improved Network Processor Synthesis System and Its Experimental Evaluations
Hideyuki MASUMOTO, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI,
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Abstract(in English) This paper proposes an improved network processor synthesis system. First, we propose an improved network processor model. The model consists of multithreaded processor cores, local memories, network oriented dedicated hardwares and multiple buses Then we extend a network processor synthesis system so that the model can be applied to it. The improved system can explore a large space of network processor design. Users can select a desirable processor by this system. We prove effectiveness of the proposed method through experimental evaluations.
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Keyword(in English) Network Processor / Multithread Processor / Performance Analysis / High-level Synthesis
Paper # VLD2004-141,ICD2004-237
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Conference Date 2005/3/4(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) An Improved Network Processor Synthesis System and Its Experimental Evaluations
Sub Title (in English)
Keyword(1) Network Processor
Keyword(2) Multithread Processor
Keyword(3) Performance Analysis
Keyword(4) High-level Synthesis
1st Author's Name Hideyuki MASUMOTO
1st Author's Affiliation Dept. of Computer Science, Waseda University()
2nd Author's Name Nozomu TOGAWA
2nd Author's Affiliation Dept. of Information and Media Sciences, The University of Kitakyushu:Advanced Research Institute for Science and Engineering, Waseda University
3rd Author's Name Masao YANAGISAWA
3rd Author's Affiliation Dept. of Computer Science, Waseda University
4th Author's Name Tatsuo OHTSUKI
4th Author's Affiliation Dept. of Computer Science, Waseda University
Date 2005/3/4
Paper # VLD2004-141,ICD2004-237
Volume (vol) vol.104
Number (no) 711
Page pp.pp.-
#Pages 6
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